1. Field of the Invention
The present invention relates generally to semiconductor circuit design, and circuit performance modeling, and, more particularly, to a system and method for improving the prediction of contact resistance variability in semiconductor device contact structures.
2. Description of the Prior Art
Variability is a serious issue for circuit designers given that performance based Circuit Limiting Yield (CLY) is now a major concern. The problem is that variability is rapidly increasing with ever shrinking technology nodes.
One major area of variability is the contact via (CA) resistance, a large component of which is layout proximity related. FIG. 1A shows the present CA Resistance Distribution Model used by circuit designers in 65 and 45 nm technologies. As shown in the plot 10 shown in FIG. 1A, based on input data comprising side-wall (SW) taper, CA height, and CA radius variations, it is seen that present CA variable resistance are assessed to range anywhere between 30 ohms and 100 ohms, in a bell curve distribution. The plot 15 shown in FIG. 1B should provide a more accurate CA Resistance Distribution Model for 65 and 45 nm technology designs given that there are many other parameters that cause variability which do not have Gaussian statistics. However, estimating the endpoints of the curve 18 and 19, particularly upper curve endpoint 19, is not always easy. These tails from non-Gaussian distributions at 19 represent specific mechanisms that (if treated as Gaussian) would make for very pessimistic designs.
The CA variability distributions shown in FIG. 1B are largely because the CA tails from layout proximity effects are quite large (bigger than the FIG. 1A numbers that are performed for regulated designs) which impact chip functionality.
Currently, it is feasible to increase the CA Size in 65 nm technology designs. As 3-sigma tolerance shows increasing it to a 50 nm Critical Dimension (CD), for example, is possible because of excellent overlay tolerances achievable. However, in 45 nm CMOS technology designs, there is limited room to increase CA size.
Particularly, FIG. 2 shows a semiconductor structure 20 including a FET device having gate structures 30, each including a gate electrode 24 having vertically formed spacer elements 31, 32, and drain and source regions 25, 26, respectively, and, further depicts a CA contact via structure 50 of tapered design, all formed on a semiconductor substrate 12. Overlay with an immersion lithography system for volume production in 45 nm is likely larger than prior 65 nm designs. Moreover, the formed spacer elements are likely to be on the order of about 20 nm in thickness from device design. Thus, as shown in FIG. 2, in an example embodiment, given a typical 95 nm distance ground-rule between the formed CA contact midline “A” and the gate vertical midline “B”, there is seen not much room to accommodate the CA structure, especially in view of the example dimensions including: the gate half-length (e.g., 15-20 nm), the spacer thickness (e.g., 10-30 nm), and, the CA structure radius of about 30-40 nm. Given a CA overlay tolerance, it is possible that the CA could cut into the spacer 32 by greater than about 10 nm which may be a problem. Moreover, the ground-rules presented would require tight tolerances on the gate design itself. That is, gates must be highly constrained; even nominal gates can be tight. Moreover, there would be presented a reliability constraint for the PC-CA corner distance.
It is thus the case that CA size determines device performance and, it is the case that in some current designs, due to CA resistance variability, manufacturers are presented with major trade-off design issue between CA opens which tend to occur at the small CD, and PC-CA shorts which tend to occur at larger CD.
Thus, while the 65 nm CMOS technology need for yield is pushing the CA size to 100 nm which is currently achievable in 65 nm ground-rules, there is not enough room for this large a CA size in 45 nm CMOS technology. For example, is shown in FIG. 2, there is depicted the limited room 39 in which the CA size in 45 nm CMOS technology ground-rules can increase. On the other hand due to material issues associated with filling a small high-aspect ratio (CA) contact hole it is difficult to fill too small a CA.
It would be highly desirable to provide an improved system and method for: (a) predicting the CA resistance variation, (b) improving the design manual values, and (c) highlighting the design implications. One could then optimize designs to either move CAs around to reduce this variability or make the designs immune to CA resistance variation.
That is, the calculated resistance from simple area calculations (RSS of SW taper, CA height, bottom CD, and resistivity) as modeled in prior art are inadequate. It is understood that in these designs, overlay assumptions are built in as CD variation. Moreover, according to the modeling techniques of prior art systems, it is assumed that all CAs in the circuit being modeled have same resistance and distributions.
Given the expected difficulty of creating yieldable CA structures, the issue of modeling CA variability is absolutely critical for CMOS circuit designers.